For a semiconductor device to function properly, it must distribute clock signals to its parallel “sequential elements,” such as flip-flops, latches, and memory, at approximately the same time. When clock signals arrive at these parallel elements at different times, the resulting “clock skew” can cause a variety of problems, including setup and hold violations, which can jeopardize the integrity of data transmitted along the device.
Large-scale semiconductor devices reduce skew by using clock distribution networks to distribute clock signals to the elements on the device. To ensure that the rise times and fall times of the clock signals meet design requirements, CMOS inverters or buffers are inserted at regular intervals. (Because inverters and buffers have similar functions in clock distribution networks, these terms are used interchangeably in this application and are also referred to as clock-drivers or clock-driving elements.) The network may diverge at multiple points. This divergence of the clock network and the insertion of CMOS inverters in the clock cause the clock skew to increase. The clock skew can increase for other reasons, such as structural problems, variations in loads along the clock distribution network, variations in process, voltages, or temperature of the inverters, and other effects in the interconnects in the clock distribution network.
One structure used to reduce clock skew is a clock mesh, which introduces interconnect elements, called cross-links, to short outputs of the inverters in the clock distribution network. These cross-links reduce the delay of the clock signals between clock-driving elements, thereby reducing clock skew, though at the expense of short-circuit power. A second structure used to reduce clock skew is a hybrid-tree mesh, such as the hybrid-tree mesh 100 of FIGS. 1A-B. The mesh portion of the hybrid-tree mesh 100, shown in FIG. 1A, includes a spine 110 supporting ribs 120 and 130, inverters 121 on the rib 120, cross-links 121 and 122 coupling clock-driving elements on the ribs 120 and 130, and a non-rectilinear clock mesh region 140. While FIG. 1A shows cross-links between elements along the ribs 120 and 130, in other structures, cross-links are inserted at other locations or combinations of locations in the clock-distribution network, such as within the clock-distribution network, at its end, or both. The mesh portion 100 is in turn driven by a hierarchical binary tree structure 150 shown in FIG. 1B, in which a clock-driving element 145 (level L2) drives 4 clock-driving elements 120A-D (level L1), and a clock-driving element 160 (level L3) drives element 145 and other elements on level L2.
While FIGS. 1A-B show several inverters, ribs, and cross-links to simplify the drawings, clock distribution networks typically have hundreds of thousands of these components directing clock signals to thousands of clock-receiving (sequential) elements. These elements represent different loads to the clock-distribution network, resulting in higher skew, as do other structures such as the non-rectilinear component 140 in FIG. 1A.
In order to reduce short-circuit power, it is important to keep the skew between the inputs of inverters whose outputs are shorted as low as possible. Thus, it is important to reduce the structural skew of the clock distribution network at design time. It may not be possible to guarantee that inverters of a clock distribution network whose outputs are shorted with a cross-link have the same load characteristics. Hence, a tune-able clock inverter is required to reduce the structural skew. The clock inverters are tuned so that those that drive large loads have large drive strengths and those that drive smaller loads have smaller driver strengths. In the last stage of a hybrid tree-mesh clock distribution network, the loads can vary substantially due to various reasons including variation in flip-flop density and non-rectilinear clock mesh regions. A tune-able clock inverter may be constructed by combining multiple base cells and connecting/disconnecting their outputs to form different effective drive strengths. This way, the input capacitance stays the same and only the output drive strength changes, thus making tuning of the clock network easier and more predictable. One way to make a tune-able clock inverter is to combine them to make one macrocell and then use that macrocell where required. One drawback to this approach is that this macrocell is treated by Electronic Design Automation (EDA) tools as a single cell through all levels of the physical design. This may require an accurate transistor level extraction and characterization of the macrocell. Also, in order to maintain the macrocell as a single cell, timing DBs, physical cell views, LVS netlists, and other collateral for this cell must be generated.